Generally, advanced process control (APC) systems are adopted to compensate overlay errors for photolithographic apparatus. The APC system receives the measured overlay errors of a production lot of semiconductor devices and calculates overlay model parameters for the production lot.
However, current APC systems merely compensate the overlay error between the current layer and a previous layer, without considering the overlay error between the actual exposed pattern and the theoretical exposed pattern of the first layer. As shown in FIG. 1, as for the first layer of the semiconductor device, the actual patterns T1, T2 respectively exposed by two lithographic apparatus are both different from the theoretical exposed pattern (indicated by bold solid lines). As shown in FIG. 2, the actual patterns L1, L2 of two different lots of same product exposed by a same lithographic apparatus are both different from the theoretical exposed pattern (indicated by bold solid lines). Furthermore, when calculating overlay model parameters for a current layer of a current production lot, the APC system only considers the differences between the current tool and the pre-tool (the layer exposed by the pre-tool is a target layer to be aligned with by the current layer) used for the current production lot, while the difference of pre-pre-tools (the layer exposed by the pre-pre-tool is previous target layer to be aligned with by layer exposed by the pre-tool) for the two production lots are not differentiated. As a result, OOS (out of spec) problems of the overlay error between the subsequent layers may occur.